描述:
module divison(clk,rst_n,start);
input clk,rst_n,start;
input [7:0] dividend; //被除数
input [7:0] divisor; //除数
output done;
output [7:0] qutient;
output [7:0] reminder;
output [15:0] sq_diff;
output [15:0] sq_temp;
reg [3:0] i;
reg [8:0] s;
reg [15:0] temp;
reg [15:0] diff;
reg isneg;
reg isdone;
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
i <= 4'd0;
s <= 9'd0;
temp <= 16'd0;
diff <= 16'd0;
isneg <= 1'b0;
isdone <=1'b0;
end
else if(start)
case(i)
0:
begin
isneg <= dividend[7]^divisor[7];
s <= divisor[7] ? {1'b1, divisor}:{1'b1,~divisor+1b'1};
temp <= dividend[7] ? {8'd0,~dividend+1'b1}:{8'd0,dividend};
diff <= 16'd0;
i <= i + 1'b1;
end
1,2,3,4,5,6,7,8:
begin
diff = temp + {s,7'd0};
if(diff[15])
temp <= {temp[14:0],1'b0};
else
begin
temp <={diff[14:0],1'b1};
i <= i +1'b1;
end
end
9:
&n