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问题： modelsim 仿真中出不来波形，麻烦看下这个testbench哪里有问题
描述:
module div_vlg_tst();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg clk_50M;
reg num;
reg rst;
// wires
wire clk_out;
// assign statements (if any)
div i1 (
// port map - connection between master ports and signals/registers
.clk_50M(clk_50M),
.clk_out(clk_out),
.num(num),
.rst(rst)
);
initial
begin
// code that executes only once
// insert code here --> begin
eachvec=0;
clk_50M=0;
rst=0;
#10 rst<=1;
num=0;
#100 num<=1;
#100 num<=3;
#100 num<=7;
// --> end
$display("Running testbench");
end
always
// optional sensitivity list
#10 clk_50M=~clk_50M;
// @(event1 or event2 or .... eventn)
begin
// code executes for every event on sensitivity list
// insert code here --> begin
// --> end
end
endmodule
描述:
quartus modelsim tquartusmodelsimtestbench
`timescale 1 ps/ 1 psmodule div_vlg_tst();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg clk_50M;
reg num;
reg rst;
// wires
wire clk_out;
// assign statements (if any)
div i1 (
// port map - connection between master ports and signals/registers
.clk_50M(clk_50M),
.clk_out(clk_out),
.num(num),
.rst(rst)
);
initial
begin
// code that executes only once
// insert code here --> begin
eachvec=0;
clk_50M=0;
rst=0;
#10 rst<=1;
num=0;
#100 num<=1;
#100 num<=3;
#100 num<=7;
// --> end
$display("Running testbench");
end
always
// optional sensitivity list
#10 clk_50M=~clk_50M;
// @(event1 or event2 or .... eventn)
begin
// code executes for every event on sensitivity list
// insert code here --> begin
// --> end
end
endmodule