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问题：初学者verilog 看不懂这些错误
描述:
报错
Error (10170): Verilog HDL syntax error at delay.v(12) near text ?
Error (10170): Verilog HDL syntax error at delay.v(12) near text "?"; expecting "end"
Error (10170): Verilog HDL syntax error at delay.v(13) near text ?
Error (10170): Verilog HDL syntax error at delay.v(13) near text "?"; expecting "end"
Error (10170): Verilog HDL syntax error at delay.v(14) near text ?
Error (10170): Verilog HDL syntax error at delay.v(14) near text "?"; expecting "end"
Error (10170): Verilog HDL syntax error at delay.v(15) near text ?
Error (10170): Verilog HDL syntax error at delay.v(15) near text "?"; expecting "end"
Error (10170): Verilog HDL syntax error at delay.v(42) near text ?
Error (10170): Verilog HDL syntax error at delay.v(42) near text "?"; expecting "endcase"
Error (10170): Verilog HDL syntax error at delay.v(43) near text ?
Error (10170): Verilog HDL syntax error at delay.v(43) near text "?"; expecting "endcase"
Error (10170): Verilog HDL syntax error at delay.v(44) near text ?
Error (10170): Verilog HDL syntax error at delay.v(45) near text ?
Error (10170): Verilog HDL syntax error at delay.v(45) near text "?"; expecting "end"
Error (10170): Verilog HDL syntax error at delay.v(46) near text ?
Error (10170): Verilog HDL syntax error at delay.v(46) near text "?"; expecting "end"
Error (10170): Verilog HDL syntax error at delay.v(47) near text ?
Error (10170): Verilog HDL syntax error at delay.v(47) near text "?"; expecting "end"
解决方案1:
描述:
verilog quartus ii
module delay(osc_in,osc_out,clk_in,clk_out,input_signal,PWM1,PWM2,PWM3,start,signal_buffer);
input osc_in,clk_in,input_signal;
output PWM1,PWM2,PWM3,start;
output osc_out,clk_out;
output signal_buffer;
reg PWM1,PWM2,PWM3,osc_out,clk_out,start;//out1,out2,out3,out4,out5,out6
reg[10:0] count;
reg signal_buffer;
initial
begin
PWM1<=1'b0;
PWM2<=1'b0;
PWM3<=1'b0;
start<=1'b0;
count<=11'd0;
signal_buffer<=1'b0;
end
always @(osc_in)
begin
if(osc_in==1)
begin
osc_out<=0;
clk_out<=0;
end
else
begin
osc_out<=1;
clk_out<=1;
end
end
always @(posedge clk_in)
begin
if(input_signal==1'b0)
begin
case(count)
11'd0: if(signal_buffer==1'b1)
start<=1'b1;
else
start<=1'b0;
11'd2: PWM3<=1'b0;
11'd4: PWM2<=1'b0;
11'd6: begin
PWM1<=1'b0;
start<=1'b0;
signal_buffer<=1'b0; //remember the input signal
end
default:
begin
PWM1<=PWM1;
PWM2<=PWM2;
PWM3<=PWM3;
end
endcase
end
else
begin
case(count)
11'd0:if(signal_buffer==1'b0)
start<=1'b1;
else
start<=1'b0;
11'd2:PWM1<=1'b1;
11'd4:PWM2<=1'b1;
11'd6:begin
PWM3<=1'b1;
start<=1'b0;
signal_buffer<=1'b1;
end
default:
begin
PWM1<=PWM1;
PWM2<=PWM2;
PWM3<=PWM3;
end
endcase
end
end
always@(posedgeclk_in or negedge start)
if(start==1'b0)
count<=11'd0;
else
if(count>11'd1500)
count<=11'd0;
else
count<=count+11'd1;
endmodule
报错
Error (10170): Verilog HDL syntax error at delay.v(12) near text ?
Error (10170): Verilog HDL syntax error at delay.v(12) near text "?"; expecting "end"
Error (10170): Verilog HDL syntax error at delay.v(13) near text ?
Error (10170): Verilog HDL syntax error at delay.v(13) near text "?"; expecting "end"
Error (10170): Verilog HDL syntax error at delay.v(14) near text ?
Error (10170): Verilog HDL syntax error at delay.v(14) near text "?"; expecting "end"
Error (10170): Verilog HDL syntax error at delay.v(15) near text ?
Error (10170): Verilog HDL syntax error at delay.v(15) near text "?"; expecting "end"
Error (10170): Verilog HDL syntax error at delay.v(42) near text ?
Error (10170): Verilog HDL syntax error at delay.v(42) near text "?"; expecting "endcase"
Error (10170): Verilog HDL syntax error at delay.v(43) near text ?
Error (10170): Verilog HDL syntax error at delay.v(43) near text "?"; expecting "endcase"
Error (10170): Verilog HDL syntax error at delay.v(44) near text ?
Error (10170): Verilog HDL syntax error at delay.v(45) near text ?
Error (10170): Verilog HDL syntax error at delay.v(45) near text "?"; expecting "end"
Error (10170): Verilog HDL syntax error at delay.v(46) near text ?
Error (10170): Verilog HDL syntax error at delay.v(46) near text "?"; expecting "end"
Error (10170): Verilog HDL syntax error at delay.v(47) near text ?
Error (10170): Verilog HDL syntax error at delay.v(47) near text "?"; expecting "end"
解决方案1:
一点一点的删 几个always没看到有什么语法错误 看看到底哪个地方错了
解决方案2:我编了下，没问题