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问题： 这段代码为什么一直报错
描述:
描述:
verilog
module mux(x,signalX,signalY,signal1,signal2);
output signal1,signal2;
input x,signalX,signalY;
reg sig1,sig2;
always @(signalX or signalY or x)
begin
if(!x)
begin
sig1 = signalX;
sig2 = signalY;
end
else
begin
sig1 = signalY;
sig2 = signalX;
end
end
assign signal1 = sig1;
assign signal2 = sig2;
endmodule
`include "mux.v"
module ddleay(xx,y,sX,sY);
parameter N = 4;
input x,sX,sY;
output y;
wire signal1,signal2,data,enable,signalX,signalY;
reg q,y;
initial
begin
q<=0;
end
assign signalX = sX;
assign signalY = sY;
genvar i;
generate
for(i=0;i<N;i=i+1)
begin:mux_loop
always @(q)
if(q!=N)
begin
mux mm(.x(x),.signalX(signalX),.signalY(signalY),.signal1(signal1),.signal2(signal2));
end
q=q+1;
end
else
begin
mux mm(.x(x),.signalX(signalX),.signalY(signalY),.signal1(data),.signal2(enable));
end
assign signalX = signal1;
assign signalY = signal1;
end
endgenerate
always @(data or enable)
begin
if(enable)
y=data;
else
y=0;
end
endmodule